Fully Buffered DIMM architecture introduces an Advanced Memory Buffer (AMB) between the memory controller and the memory module. Unlike the parallel bus architecture of traditional DRAMs, an FB-DIMM has a serial interface between the memory controller and the AMB. This enables an increase to the width of the memory without increasing the pin count of the memory controller beyond a feasible level. With this architecture, the memory controller does not write to the memory module directly, rather it is done via the AMB. The AMB can thus compensate for signal deterioration by buffering and resending the signal. In addition, the AMB can also offer error correction, without posing any overhead on the processor or the memory controller. It can also use the Bit Lane Failover Correction feature to identify bad data paths and remove them from operation, which dramatically reduces command/address errors. Also, since reads and writes are buffered, they can be done in parallel by the memory controller. This allows simpler interconnects, more memory bandwidth, and (in theory) hardware-agnostic memory controller chips (such as DDR2 and DDR3) which can be used interchangeably. The downside to this approach is that it introduces latency to the memory request.